Wednesday, 23 August, 2017

IBM Reveals World's First 5nm Chip With 30bn Transistors

Above IBM researcher holds a wafer full of 5-nanometer test Above IBM researcher holds a wafer full of 5-nanometer test
Cecilia Poole | 19 June, 2017, 02:14

Key to the innovation is halving the size of the transistor gates on current chips from 10 nanometres to 5 nanometres (nm) - more gates means more power and more efficiency, and that's going to help in everything from self-driving cars to smartphones.

Moore's law, coined first in 1970, is the observation that the number of transistors that can be accommodated on a single chip doubles nearly every two years.

"The work is to continue to push and innovate so we can be on par or better than Moore's Law", said Khare.

The 5nm process was demonstrated by producing silicon nanosheet transistors at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering NanoTech Complex in Albany, NY.

IBM says these chips will be much faster than anything we have today, and that's a given.

IBM, in collaboration with Samsung and GlobalFoundries, announced on Monday it's developed the world's first 5 nanometer (nm) silicon chip with 30 billion transistors. Not only that, but the 5nm chips also promise a 40% increase in performance or a 75% reduction in power consumption over the 10nm process technology now in use by Samsung.

The approach they used is called Extreme Ultraviolet (EUV) lithography. In some background information to the development, we are told that IBM has been exploring nanosheet semiconductor technology for more than 10 years. IBM's previous 7 nm chip packed 20 billion transistors.

IBM sees the technique helping its own cognitive computing efforts as well as the Internet of Things and other "data-intensive" tasks.

IBM is saying these chips will be 40 percent quicker with the same power draw, which means they will save 75 percent in power when running at the same speed as today's chips. The nanosheet transistor sends electrons through four gates, whereas the current-generation FinFET transistor design that sends electrons through three gates. This not only allows IBM to cram even more in a tiny space but also offers some flexibility to change the width of the nanosheets even in a single manufacturing process.

IBM also said the improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

The heart of the R&D advance is a new gate-all-around architecture that employs stacked silicon nanosheets, replacing the FinFET structure used in today's leading processors. The reduction in chip size has, however, seen to the further thinning out of the chips making the third dimension irrelevant.

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